The main issue which continues to plague integrated circuit design including system-on-a-chip (SoC) technologies is timing. In order to address the issue of timing, a number of different static timing analysis tools including Primetime® (Primetime® is a trademark registered to SYNOPSYS) have been developed. Primetime® is a full-chip, gate-level static timing analysis tool which is capable of analyzing millions of gates in a short time period and thus, allowing multiple analysis runs in a given day. A static timing analysis tool such as Primetime® analyzes timing errors and noise due to crosstalk as well as IR drop with complex clocking schemes including gated clocks. Further, a static timing analysis tool may include a timing model extraction feature which may be used to increase designer productivity by reducing analysis runtime and memory usage. For example, Primetime® includes a timing model extraction feature that automatically generates a high-level model from a gate-level netlist. In addition, static timing analysis tools may support CRPR in order to remove artificially-induced pessimism from a timing report between a launching and capturing device. Typically, CRPR is most applicable in the on-chip variation (OCV) mode which is the mode associated with the greatest timing variations. In the absence of CRPR, the actual timing properties of a circuit may be skewed by delay variation in clock networks and thus, led to the belief that the circuit may operate at a lower frequency than the actual silicon implementation.
Although present static timing analysis tools have improved integrated circuit performance, such systems are limited under certain circumstances. For example, it is often problematic to get the ETMs to match the timing of the gate level netlist. The ETM may be a timing abstraction which hides the gate level netlist from the customer. However, such configuration also results in a loss in information including information regarding the exact clock delay of a path versus a data delay.
Therefore, it would be desirable to provide a method for enabling clock CRPR in ETMs which overcomes the aforementioned limitations associated with the present methods for CRPR.